Semiconductor electronic devices are made in foundries, of which there are over a hundred worldwide (operated by approximately two dozen or so semiconductor companies adopting a foundry model). Fabrication of large-scale integrated semiconductor electronic devices requires multiple process steps and mask layers that define etching and deposition patterns (e.g., for photoresists), dopant implants, and metallization. A semiconductor foundry may employ a particular set of process steps and mask layers for a given semiconductor device, and process steps/mask layers can differ significantly for different types of semiconductor devices (as well as similar devices made by different foundries). A particular set of process steps and mask layers employed by a given foundry to fabricate any of a variety of semiconductor devices is generally referred to as a “semiconductor manufacturing process technology” (or simply “semiconductor technology”). For fabrication of silicon-based Complimentary-Metal-Oxide-Semiconductor (CMOS) devices, different manufacturing process technologies are sometimes commonly referred to as “CMOS technology nodes.” Some common examples of conventional CMOS technology nodes include a 45-nm silicon-on-insulator (SOI) process technology available from IBM (i.e., the IBM SOI12S0 45-nm technology), as well as the IBM SOI13S0 32 nm technology and the IBM 10LPE technology.
For each different semiconductor technology, a set of “design rules” is provided that includes a series of parameters specifying certain geometric and connectivity restrictions for manufacturing semiconductor devices. Such design rules are based on the available process steps and mask layers in a particular semiconductor technology, and provide sufficient margins to account for variability in the process steps used in the technology. Thus, design rules define allowed semiconductor design patterns to be converted to mask designs for the physical layout of a device in a given semiconductor technology. The specification of such technology-dependent design rules ensures reasonably predictable and sufficiently high yields for semiconductor device manufacturing using the given semiconductor technology (e.g., billions of nanoscale components can be fabricated simultaneously with high yield and performance).
Some examples of common design rules employed in a variety of conventional semiconductor technologies include “single layer rules” that specify geometric restrictions and/or restrictions on various connection between elements on a given layer of a multi-layer semiconductor design. Examples of single layer rules include a “minimum size rule” that defines one or more minimum dimensions of any feature or object in a given layer of the design (e.g., a “width rule” that specifies the minimum width, in a plane parallel to the semiconductor substrate, of a feature or object in the design), and a “minimum spacing rule” that specifies a minimum distance between two adjacent features/objects in a given layer. Other examples of single layer rules relate to polygon-shaped elements, and include minimum/maximum area and allowed orientations of polygon edges. Other types of conventional design rules include “two layer rules” (specifying certain relationships that must exist between two layers, such as distance, extension or overlap between two or more layers). Design rule sets have become increasingly more complex with successive generations of semiconductor technologies.
One area of developing research in computing relates to monolithic integration of million-to-billion-transistor circuits with photonic components as an enabling technology for high performance computers (HPC). Generally speaking, “photonic components” refer to various devices employed for light (or photon) generation or emission, transmission or propagation, modulation (e.g., signal processing, switching, filtering, wavelength and/or mode selectivity, amplification), and detection. Optical processing techniques enabled by photonic components can accelerate computation in HPCs by performing processor-intensive tasks at significantly faster rates and with a significant reduction in energy consumption as compared to purely electronic processing techniques. Accordingly, the integration of photonic components and electronic components for computing and other applications is an active area of research endeavor.
In connection with photonic detection devices (referred to generally as “photodetectors”), some such devices may be realized in silicon-based fabrication technologies (e.g., in which photonic detection is based on mid band gap absorption in doped or poly-crystalline silicon waveguides, or by internal photoemission absorption using Schottky junctions). Other investigated approaches for design and fabrication of photodetectors rely on the incorporation of pure germanium on silicon, in which the germanium facilitates photocarrier generation in response to incident photons impinging on the photodetector. However, germanium and other specialized materials, processes and/or geometries that are particularly useful for fabrication of photonics components generally are not readily available in conventional semiconductor manufacturing process technologies employed in advanced electronic foundries. For example, one limited demonstration of integrating germanium photonic components with electronic components involved a modified CMOS technology flow based on 90 nm or older CMOS nodes; however, these CMOS technology nodes already are obsolete for building HPC microprocessors. Moreover, the modifications required of conventional semiconductor technologies to accommodate photonic components generally involve costly process development that in turn creates challenges in maintaining fabrication yield.